Typically, an integrated circuit (IC) such as a microcomputer has a sleep mode (i.e., low power consumption mode) that reduces power consumption. The sleep mode stops supply of clock signals to most of logic circuits in the IC so that the logic circuits stop operation.
A manufacturing process technology of the IC is advanced and the IC is manufactured with a finer (e.g., 90 nm) manufacturing process. In other words, the number of transistors per chip is increased so that the transistors have a reduced minimum line-width. Such an IC operates at a lower voltage and the transistors have a reduced threshold voltage. Therefore, a leak current occurs regardless of whether the logic circuits operate and the power consumption in the sleep mode is increased.
A semiconductor device disclosed in U.S. Pat. No. 6,657,911 corresponding to JP-2003-132683A includes a logic circuit, a SRAM circuit for storing data processed by the logic circuit, and a control circuit for controlling a substrate bias applied to the SRAM circuit. In a sleep mode of the semiconductor device, a power supply voltage supplied to the logic circuit is stopped and the control circuit controls the substrate bias to reduce a leak current.
The control circuit for controlling the substrate bias is constructed with an analog circuit such as a charge pump circuit. However, an automatic layout generator for an analog circuit has not been advanced yet. Therefore, when a manufacturing process of the semiconductor device is changed (e.g., from 90 nm to 65 nm), the semiconductor device needs to be manually redesigned.